1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a FinFET device with a unique gate configuration, and the resulting FinFET semiconductor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of so-called metal oxide field effect transistors (MOSFETs or FETs). A transistor includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region that is separated therefrom by a gate insulation layer. Current flow between the source and drain regions of the FET device is controlled by controlling the voltage applied to the gate electrode.
Transistors come in a variety of configurations. A conventional FET is a planar device, wherein the transistor is formed in and above an active region having a substantially planar upper surface. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12. The device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap layer 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 are the source/drain regions of the device 10.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET device, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces undesirable short channel effects. When an appropriate voltage is applied to the gate electrode 16 of a FinFET device 10, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin (for a tri-gate device), form a surface inversion layer or “channel” that permits current conduction between the source and drain regions of the device 10. For a dual-gate device, an insulating material is positioned above the upper surface of the fins 14 such that the channel regions are only formed along the sidewalls of the fins 14. Due to the configuration of the fin and the configuration of the gate structure that wraps around three sides of the fin, there is better electrostatic control of the “fin” channel regions on FinFET devices.
Another known transistor device is typically referred to as a nanowire device. In a nanowire device, at least the channel region of the device is comprised of one or more very small diameter, wire-like semiconductor structures. As with the other types of transistor devices discussed above, current flow through a nanowire device is controlled by setting the voltage applied to the gate electrode. When an appropriate voltage is applied to the gate electrode, the channel region of the nanowire device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region, i.e., current flows through the nanowire structure. In a nanowire device, the gate structure is typically formed such that it wraps around the nanowire channel structure. Accordingly, such a nanowire device has even better gate control characteristics than that of a tri-gate FinFET device. Unfortunately, the process flows for making nanowire devices can be very complex and time consuming, thereby leading to increased processing complexity and increased manufacturing costs.
However, as device dimensions continue to shrink, device designers are compelled to look for novel designs of transistors that may provide better electrostatic control of the channel region of the devices. The present disclosure is directed to various methods of forming a FinFET device with a unique gate configuration, and the resulting FinFET semiconductor device, that may avoid, or at least reduce, the effects of one or more of the problems identified above.